Nexperia B.V. 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state 74ALVT162823DGGY

Description
The 74ALVT162823 is an 18-bit positive-edge triggered D-type flip-flop with 30 Ω termination resistors, 3-state outputs reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. Features and benefits Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops 5 V I/O compatible Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state Power-up reset Output capability: +12 mA to −12 mA Outputs include series resistance of 30 Ω making external termination resistors unnecessary Latch-up protection: JESD78: exceeds 500 mA ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C
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18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state - 74ALVT162823DGGY - Nexperia B.V.
Nijmegen, Netherlands
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state
74ALVT162823DGGY
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state 74ALVT162823DGGY
The 74ALVT162823 is an 18-bit positive-edge triggered D-type flip-flop with 30 Ω termination resistors, 3-state outputs reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. Features and benefits Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops 5 V I/O compatible Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state Power-up reset Output capability: +12 mA to −12 mA Outputs include series resistance of 30 Ω making external termination resistors unnecessary Latch-up protection: JESD78: exceeds 500 mA ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C

The 74ALVT162823 is an 18-bit positive-edge triggered D-type flip-flop with 30 Ω termination resistors, 3-state outputs reset and enable.

The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs.

Features and benefits

  • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
  • 5 V I/O compatible
  • Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors
  • Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
  • Live insertion and extraction permitted
  • Power-up 3-state
  • Power-up reset
  • Output capability: +12 mA to −12 mA
  • Outputs include series resistance of 30 Ω making external termination resistors unnecessary
  • Latch-up protection:
    • JESD78: exceeds 500 mA
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C
Supplier's Site Datasheet
Flip Flops - 1727-74ALVT162823DGGYCT-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 9BIT 56TSSOP

IC FF D-TYPE DUAL 9BIT 56TSSOP

Buy Now Datasheet
Flip Flops - 1727-74ALVT162823DGGYTR-ND - DigiKey
Thief River Falls, MN, United States
"Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240"", 6.10mm Width)"

"Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240"", 6.10mm Width)"

Buy Now Datasheet
Flip Flops - 1727-74ALVT162823DGGYDKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 9BIT 56TSSOP

IC FF D-TYPE DUAL 9BIT 56TSSOP

Buy Now Datasheet
Logic - Flip Flops - 74ALVT162823DGGY - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
74ALVT162823DGGY
Logic - Flip Flops 74ALVT162823DGGY
Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240

Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240

Supplier's Site Datasheet
Flip Flops - 74ALVT162823DGGY - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)

Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74ALVT162823DGGY - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74ALVT162823DGGY
Integrated Circuits (ICs) - Logic - Flip Flops 74ALVT162823DGGY
IC FF D-TYPE DUAL 9BIT 56TSSOP

IC FF D-TYPE DUAL 9BIT 56TSSOP

Supplier's Site
Logic - Flip Flops - 74ALVT162823DGGY - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74ALVT162823DGGY
Logic - Flip Flops 74ALVT162823DGGY
IC FF D-TYPE DUAL 9BIT 56TSSOP

IC FF D-TYPE DUAL 9BIT 56TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Nova Technology(HK) Co.,Ltd Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVT162823DGGY 1727-74ALVT162823DGGYCT-ND 74ALVT162823DGGY 74ALVT162823DGGY 74ALVT162823DGGY 74ALVT162823DGGY
Product Name 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state Flip Flops Logic - Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 2.3 - 3.6 2.3V ~ 2.7V, 3V ~ 3.6V 3V; 3.6V; 2.3V ~ 2.7V, 3V ~ 3.6V
Output Characteristics 3-State; OE 3-State
Features ESD Protection
Propagation Delay 3 ns 4.4 ns
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