The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-state outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE0 and 1OE1 or 2OE0 and 2OE1) inputs must both be active. If either output enable input is high, the outputs of that 10-bit buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
Features and benefits
Wide supply voltage range of 1.2 V to 3.6 V
CMOS low power consumption
MultiByte flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels (2.7 V to 3.6 V)
Bus hold on data inputs
Output drive capability 50 Ω transmission lines at 85 °C
Current drive ±24 mA at 3.0 V
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with 3-state outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE0 and 1OE1 or 2OE0 and 2OE1) inputs must both be active. If either output enable input is high, the outputs of that 10-bit buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
Features and benefits
- Wide supply voltage range of 1.2 V to 3.6 V
- CMOS low power consumption
- MultiByte flow-through standard pin-out architecture
- Low inductance multiple VCC and GND pins for minimum noise and ground bounce
- Direct interface with TTL levels (2.7 V to 3.6 V)
- Bus hold on data inputs
- Output drive capability 50 Ω transmission lines at 85 °C
- Current drive ±24 mA at 3.0 V
- Complies with JEDEC standards:
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
