Nexperia B.V. 18-bit universal bus transceiver; 3-state 74ALVCH16501DGGY

The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW). This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power dissipation
• Direct interface with TTL levels
• Current drive ±24 mA at V_CC = 3.0 V
• Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode
• Bus hold on all data inputs
• Output drive capability 50 Ω transmission lines at 85 °C
• 3-state non-inverting outputs for bus-oriented applications
• Latch-up performance exceeds 100 mA per JESD78 Class II.A
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C/JESD36 (2.7 V to 3.6 V)

Universal Bus Transceiver 18-Bit 56-TSSOP

IC UNIV BUS TXRX 18BIT 56TSSOP

Universal Bus Transceiver 18-Bit 56-TSSOP

Universal Bus Transceiver 18-Bit 56-TSSOP