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Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74BQ,115

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Dual D-type flip-flop with set and reset; positive-edge trigger - 74ALVC74BQ,115 - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74ALVC74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74BQ,115
The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V
  • CMOS low power dissipation
  • Overvoltage tolerant inputs to 3.6 V
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD78 Class II.A
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 to 1.95 V)
    • JESD8-5 (2.3 to 2.7 V)
    • JESD8C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-6798-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6798-6-ND
Flip Flops 1727-6798-6-ND
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Supplier's Site Datasheet
Flip Flops - 1727-6798-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6798-1-ND
Flip Flops 1727-6798-1-ND
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Supplier's Site Datasheet
Flip Flops - 1727-6798-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6798-2-ND
Flip Flops 1727-6798-2-ND
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Supplier's Site Datasheet
Flip Flops - 74ALVC74BQ,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74ALVC74BQ,115
Flip Flops 74ALVC74BQ,115
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Supplier's Site Datasheet
 - 74ALVC74BQ,115 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74ALVC74BQ - D Flip-Flop, ALVC/VCX/A Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PQCC14

Nexperia 74ALVC74BQ - D Flip-Flop, ALVC/VCX/A Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PQCC14

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74ALVC74BQ,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74ALVC74BQ,115
Integrated Circuits (ICs) - Logic - Flip Flops 74ALVC74BQ,115
IC FF D-TYPE DUAL 1BIT 14DHVQFN

IC FF D-TYPE DUAL 1BIT 14DHVQFN

Supplier's Site
Yishun, Singapore
Logic - Logic - Flip Flops - 74ALVC74BQ,115
1007674-74ALVC74BQ,115
Logic - Logic - Flip Flops - 74ALVC74BQ,115 1007674-74ALVC74BQ,115
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1007674-74ALVC74BQ,1 15 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Differential Current - Output High, Low: 24mA, 24mA Number of Elements: 2 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 3.8ns @ 3.3V, 50pF Trigger Type: Positive Edge Current - Quiescent: 10μA Input Capacitance: 3.5pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 85°C (TA) Dimension: 14-VFQFN Exposed Pad Purpose: Set(Preset) and Reset Supply Voltage - Operating: 1.65 V to 3.6 V Max Frequency: 425MHz Popularity: Medium Fake Threat In the Open Market: 51 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1007674-74ALVC74BQ,115
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Differential
Current - Output High, Low: 24mA, 24mA
Number of Elements: 2
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 3.8ns @ 3.3V, 50pF
Trigger Type: Positive Edge
Current - Quiescent: 10μA
Input Capacitance: 3.5pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 85°C (TA)
Dimension: 14-VFQFN Exposed Pad
Purpose: Set(Preset) and Reset
Supply Voltage - Operating: 1.65 V to 3.6 V
Max Frequency: 425MHz
Popularity: Medium
Fake Threat In the Open Market: 51 pct.
Supply and Demand Status: Balance

Supplier's Site Datasheet
Logic - Flip Flops - 74ALVC74BQ,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74ALVC74BQ,115
Logic - Flip Flops 74ALVC74BQ,115
IC FF D-TYPE DUAL 1BIT 14DHVQFN

IC FF D-TYPE DUAL 1BIT 14DHVQFN

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Quarktwin Technology Ltd. Rochester Electronics Shenzhen Shengyu Electronics Technology Limited Win Source Electronics Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVC74BQ,115 1727-6798-6-ND 74ALVC74BQ,115 74ALVC74BQ,115 74ALVC74BQ,115 1007674-74ALVC74BQ,115 74ALVC74BQ,115
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Logic - Flip Flops - 74ALVC74BQ,115 Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered; Positive Edge
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.65 - 3.6 1.65V ~ 3.6V 3.6V; 1.65V ~ 3.6V 1.65 V ~ 3.6 V
Features ESD Protection
Propagation Delay 2.3 ns 3.8 ns 3.8 ns
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