Nexperia B.V. Quad 2-input NAND gate 74ALVC00PW,118

Description
The 74ALVC00 is a quad 2-input NAND gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Quad 2-input NAND gate - 74ALVC00PW,118 - Nexperia B.V.
    Nexperia B.V.
  • 74ALVC00PW,118 - Rochester Electronics
    Rochester Electronics
  • Gates and Inverters - 1727-74ALVC00PW,118TR-ND - DigiKey
    DigiKey
  • Logic - Gates and Inverters - 74ALVC00PW,118 - Lingto Electronic Limited
    Lingto Electronic Limited
  • Gates and Inverters - 74ALVC00PW,118 - Quarktwin Technology Ltd.
    Quarktwin Technology Ltd.
Request a Quote Datasheet
Description
The 74ALVC00 is a quad 2-input NAND gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Quad 2-input NAND gate - 74ALVC00PW,118 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Quad 2-input NAND gate
74ALVC00PW,118
Quad 2-input NAND gate 74ALVC00PW,118
The 74ALVC00 is a quad 2-input NAND gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V CMOS low power dissipation Overvoltage tolerant inputs to 3.6 V Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA per JESD78 Class II.A Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74ALVC00 is a quad 2-input NAND gate.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V
  • CMOS low power dissipation
  • Overvoltage tolerant inputs to 3.6 V
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD78 Class II.A
  • Complies with JEDEC standards:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
- 74ALVC00PW,118 - Rochester Electronics
Rochester Electronics
Newburyport, MA, United States
74ALVC00PW,118
74ALVC00PW,118
NAND Gate, ALVC/VCX/A Series, 4-Func, 2-Input, CMOS, PDSO14

NAND Gate, ALVC/VCX/A Series, 4-Func, 2-Input, CMOS, PDSO14

Supplier's Site Datasheet
Gates and Inverters - 1727-74ALVC00PW,118TR-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74ALVC00PW,118TR-ND
Gates and Inverters 1727-74ALVC00PW,118TR-ND
NAND Gate IC 4 Channel 14-TSSOP

NAND Gate IC 4 Channel 14-TSSOP

Buy Now Datasheet
Logic - Gates and Inverters - 74ALVC00PW,118 - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Gates and Inverters
74ALVC00PW,118
Logic - Gates and Inverters 74ALVC00PW,118
IC GATE NAND 4CH 2-INP 14TSSOP

IC GATE NAND 4CH 2-INP 14TSSOP

Supplier's Site Datasheet
Gates and Inverters - 74ALVC00PW,118 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74ALVC00PW,118
Gates and Inverters 74ALVC00PW,118
NAND Gate IC 4 Channel 14-TSSOP

NAND Gate IC 4 Channel 14-TSSOP

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. Rochester Electronics DigiKey Lingto Electronic Limited Quarktwin Technology Ltd.
Product Category Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates
Product Number 74ALVC00PW,118 74ALVC00PW,118 1727-74ALVC00PW,118TR-ND 74ALVC00PW,118 74ALVC00PW,118
Product Name Quad 2-input NAND gate Gates and Inverters Logic - Gates and Inverters Gates and Inverters
Gate Type NAND AND; NAND NAND NOT; NAND NAND; NAND Gate
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.65 - 3.6 1.65V ~ 3.6V 1.7V ~ 2V (Low), 0.7V ~ 0.8V (High) 3.6V; 1.65V ~ 3.6V
Logic Family TTL; TTL CMOS
Propagation Delay 2.1 ns 2.1 ns
Operating Temperature -40 to 85 C (-40 to 185 F) -40 to 85 C (-40 to 185 F) -40 to 85 C (-40 to 185 F)
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