Nexperia B.V. Octal D-type transparent latch; 3-state 74AHCT573BQ,115

Description
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. Features and benefits Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Common 3-state output enable input Functionally identical to the 74AHC373; 74AHCT373 Input levels: For 74AHC573: CMOS input level For 74AHCT573: TTL input level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Description
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. Features and benefits Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Common 3-state output enable input Functionally identical to the 74AHC373; 74AHCT373 Input levels: For 74AHC573: CMOS input level For 74AHCT573: TTL input level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Octal D-type transparent latch; 3-state - 74AHCT573BQ,115 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type transparent latch; 3-state
74AHCT573BQ,115
Octal D-type transparent latch; 3-state 74AHCT573BQ,115
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. Features and benefits Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Common 3-state output enable input Functionally identical to the 74AHC373; 74AHCT373 Input levels: For 74AHC573: CMOS input level For 74AHCT573: TTL input level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.

Features and benefits

  • Wide supply voltage range from 2.0 V to 5.5 V
  • Balanced propagation delays
  • All inputs have Schmitt-trigger action
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • CMOS low power dissipation
  • Common 3-state output enable input
  • Functionally identical to the 74AHC373; 74AHCT373
  • Input levels:
    • For 74AHC573: CMOS input level
    • For 74AHCT573: TTL input level
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Latches - 1727-74AHCT573BQ,115CT-ND - DigiKey
Thief River Falls, MN, United States
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Latches - 1727-74AHCT573BQ,115TR-ND - DigiKey
Thief River Falls, MN, United States
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Latches - 74AHCT573BQ,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Latches - 74AHCT573BQ,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Latches
74AHCT573BQ,115
Integrated Circuits (ICs) - Logic - Latches 74AHCT573BQ,115
IC D-TYPE TRANSP SGL 8:8 20HVQFN

IC D-TYPE TRANSP SGL 8:8 20HVQFN

Supplier's Site
Logic - Latches - 74AHCT573BQ,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Latches
74AHCT573BQ,115
Logic - Latches 74AHCT573BQ,115
IC TRANSP LATCH OCT D 20DHVQFN

IC TRANSP LATCH OCT D 20DHVQFN

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited
Product Category Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches
Product Number 74AHCT573BQ,115 1727-74AHCT573BQ,115CT-ND 74AHCT573BQ,115 74AHCT573BQ,115 74AHCT573BQ,115
Product Name Octal D-type transparent latch; 3-state Latches Latches Integrated Circuits (ICs) - Logic - Latches Logic - Latches
Latch Type Transparent-D Transparent-D D; Transparent-D
Output Characteristics 3-State 3-State
Features ESD Protection
Supply Voltage +7.0 4.5V ~ 5.5V 4.5V ~ 5.5V
Package Type SOT764-1 SOT764-1 20-VFQFN Exposed Pad 20-VFQFN Exposed Pad
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