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Nexperia B.V. 3-to-8 line decoder/demultiplexer; inverting 74AHC138PW-Q100J

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3-to-8 line decoder/demultiplexer; inverting - 74AHC138PW-Q100J - Nexperia B.V.
Nijmegen, Netherlands
3-to-8 line decoder/demultiplexer; inverting
74AHC138PW-Q100J
3-to-8 line decoder/demultiplexer; inverting 74AHC138PW-Q100J
The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138-Q100; 74AHCT138-Q100 is a 3-to-8 line decoder/demultiplexe r. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74AHC138-Q100; 74AHCT138-Q100 devices and one inverter. The 74AHC138-Q100; 74AHCT138-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Balanced propagation delays All inputs have Schmitt-trigger action Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Inputs accepts voltages higher than VCC For 74AHC138-Q100 only: operates with CMOS input levels For 74AHCT138-Q100 only: operates with TTL input levels ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC138-Q100; 74AHCT138-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected.

There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74AHC138-Q100; 74AHCT138-Q100 devices and one inverter. The 74AHC138-Q100; 74AHCT138-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Balanced propagation delays
  • All inputs have Schmitt-trigger action
  • Demultiplexing capability
  • Multiple input enable for easy expansion
  • Ideal for memory chip select decoding
  • Inputs accepts voltages higher than VCC
  • For 74AHC138-Q100 only: operates with CMOS input levels
  • For 74AHCT138-Q100 only: operates with TTL input levels
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Supplier's Site Datasheet
 - 74AHC138PW-Q100J - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AHC138PW-Q100 - Decoder/Driver, AHC/VHC/H/U/V Series, Inverted Output, CMOS, TSSOP16

Nexperia 74AHC138PW-Q100 - Decoder/Driver, AHC/VHC/H/U/V Series, Inverted Output, CMOS, TSSOP16

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Rochester Electronics
Product Category Logic Decoders and Demultiplexers Logic Decoders and Demultiplexers
Product Number 74AHC138PW-Q100J 74AHC138PW-Q100J
Product Name 3-to-8 line decoder/demultiplexer; inverting
Function Decoder/Demultiplexer Decoder
Input Lines 3
Output Lines 8
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 5.5
Features ESD Protection
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