The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards. Measuring just 5 mm (millimeters) x 5 mm, the ZL30108 DPLL addresses dense line card "real estate" constraints. The device may be used in combination with Microchip's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment. For example, the ZL30108 DPLL and ZL30415 analog PLL provide an easy-to-implement, compact solution for OC-12/STM-4 line cards.
Additional Features
Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
Provides a 19.44 MHz (SONET/SDH) clock output
Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
Provides automatic entry into Holdover and return from Holdover
Hitless reference switching
Provides lock and accurate reference fail indication
Loop filter bandwidth of 29 Hz or 14 Hz
Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
Ultra Compact (5 mm x 5 mm) 32-pin QFN package
The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards. Measuring just 5 mm (millimeters) x 5 mm, the ZL30108 DPLL addresses dense line card "real estate" constraints. The device may be used in combination with Microchip's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment. For example, the ZL30108 DPLL and ZL30415 analog PLL provide an easy-to-implement, compact solution for OC-12/STM-4 line cards.
Additional Features
- Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
- Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
- Provides a 19.44 MHz (SONET/SDH) clock output
- Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
- Provides automatic entry into Holdover and return from Holdover
- Hitless reference switching
- Provides lock and accurate reference fail indication
- Loop filter bandwidth of 29 Hz or 14 Hz
- Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
- Ultra Compact (5 mm x 5 mm) 32-pin QFN package
