Microchip Technology, Inc. PSX 68xG4 Gen 4 Programmable PCIe Switch PM41068

The Switchtec Gen 4 PM41068 PSX programmable PCIe switch comprises programmable and high-reliability switches that supports 68 lanes, 36 ports, 18 virtual switch partitions, 34 Non-Transparent Bridges (NTBs) and hot- and surprise-plug controllers for each port. PSX switches feature advanced error containment, comprehensive diagnostics and debug capabilities, end-to-end data integrity protection, high-quality, low power SERDES and secure boot image authentication. Typical applications for the PSX family include PCIe SSD enclosures, Flash arrays, multi-host architectures, high-density servers, blade servers, pooled storage/compute and applications that require customized, high-reliability PCIe switching. Additional Features High-reliability PCIe with robust error containment, hot- and surprise-plug controllers per port, end-to-end data integrity protection, high-quality, low-power SERDES PSX Software Development Kit (SDK) enables customerd ifferentiated solutions in areas such as error containment and surprise-plug Integrated enclosure management processor, I/O interfaces, and SDK for enclosure management firmware development Significant power, cost and board space savings with support for 36 ports, 34 NTBs, and 18 virtual switch partitions and flexible x1, x2, x4, x8, and x16 port bifurcation with norestrictions on configuring ports as either upstream or downstream, or on mapping ports to NTBs NVMe-MI enclosure management for integrated NVMe controller, in-band management supporting SES and native NVMe enclosure management stack and out-of-band management supporting MCTP through I2C Secure system solution with boot image authentication High-Performance Non-blocking Switches 68-lane variant Ports bifurcate to ×1*/×2/×4/×8/×16 lanes 34 NTBs assignable to any port Logical non-transparent (NT) interconnect allows for larger topologies Supports 1+1 and N+1 failover mechanisms DMA Controller High-performance, ultra-low latency DMA engine Error Containment Advanced error reporting (AER) on all ports Downstream port containment (DPC) on all downstream ports Completion timeout synthesis (CTS) to prevent an error state in an upstream host due to incomplete non-posted transactions Upstream Error Containment (UEC), a programmable feature that prevents errors from propagating upstream GPIOs configurable for different cable/connector standards Hot- and surprise-plug controllers per port PCIe Interfaces Passive, managed, and optical cables SFF-8644, SFF-8643, SFF-8639, OCuLink and other connectors Diagnostics and Debug Real-time eye capture External loopback Errors, statistics, and performance counters Peripheral I/O Interfaces Up to 11 Two-Wire Interfaces (TWIs) with SMBus support Up to 4 SFF-8485-compliant SGPIO ports 10/100 Ethernet MAC port (MII/RMII) Up to 4 UARTs High-Speed I/O PCIe Gen 4 16 GT/s Supports OCuLink cabling, CEM ×16 slots, and other interfaces Manual PHY configuration for optical Power Management Active State Power Management (ASPM) Software-controlled power management ChipLink Diagnostic Tools Extensive debug, diagnostics, configuration, and analysis tools with an intuitive GUI Access to configuration data, management capabilities, and signal integrity analysis tools (such as real-time eye capture) Evaluation Kit The PM42100-KIT Switchtec Gen 4 PCIe switch evaluation kit is a device evaluation environment that supports multiple interfaces