Lansdale Semiconductor, Inc. Dual 2-Bit Adder/Subtractor 10580/E,F

Description
The 10500/10100 series of emitter-coupled logic is the fastest logic technology available for practical use. A conventional planar process is used for the 10K ECL series with a density of about ten gates per mm2 and a delay of 2 ns per gate.
Description
The 10500/10100 series of emitter-coupled logic is the fastest logic technology available for practical use. A conventional planar process is used for the 10K ECL series with a density of about ten gates per mm2 and a delay of 2 ns per gate.

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Dual 2-Bit Adder/Subtractor - 10580/E,F - Lansdale Semiconductor, Inc.
Phoenix, AZ, USA
Dual 2-Bit Adder/Subtractor
10580/E,F
Dual 2-Bit Adder/Subtractor 10580/E,F
The 10500/10100 series of emitter-coupled logic is the fastest logic technology available for practical use. A conventional planar process is used for the 10K ECL series with a density of about ten gates per mm2 and a delay of 2 ns per gate.

The 10500/10100 series of emitter-coupled logic is the fastest logic technology available for practical use. A conventional planar process is used for the 10K ECL series with a density of about ten gates per mm2 and a delay of 2 ns per gate.

Technical Specifications

  Lansdale Semiconductor, Inc.
Product Category Arithmetic Logic Units (ALU)
Product Number 10580/E,F
Product Name Dual 2-Bit Adder/Subtractor
Number of Bits 2
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