Allied Electronics, Inc. Datasheets for Logic Gates
Logic gates are electronic circuits that combine digital signals according to boolean algebra.
Logic Gates: Learn more
| Product Name | Notes |
|---|---|
| -0.5 to +7 V, +⁄- 0.1 uA (Max.), -0.5 to VCC + 0.5 V, 1 uA (Max.), Hex Schmitt Inverter High speed High noise immunity Low power dissipation The M74HC14... | |
| -0.5 to +7 V, -0.5 to VCC + 0.5 V, +⁄- 0.1 uA (Max.), 1 uA (Max.), 8-Input NOR⁄OR Gate High speed Low power dissipation Balanced propagation delay High noise... | |
| -0.5 to +7 V, 750 mW, -0.5 to VCC + 0.5 V, 1 uA (Max.), QUAD 2-Input Schmitt NAND Gate High speed High noise immunity Low power dissipation Balanced propagation... | |
| -0.5 to 20 V Supply Voltage, -65 to +125 °C Operating Ambient Temperature, CMOS AND Gates 100% tested for quiescent current at 20 V Maximum input current of 1 μA... | |
| 13 ns (Typ.) Propagation Delay Time, 3.5 pF (Typ.) Input Capacitance, Dual 4-input NAND Gate Output capability: standard ICC category: SSI The 74HC⁄HCT20 are high-speed Si-gate CMOS devices and are... | |
| 14-Lead PDIP Package, 5 V (Typ.) Supply Voltage, 500 mW Power Dissipation, Quad 2-input NAND Gate Complies with JEDEC Standard No. 8-1A ESD protection The 74HCT00 are high-speed Si-gate CMOS... | |
| 2 uA (Max.) Quiescent Current, Quad 2-input AND Gate Complies with JEDEC standard no. 8-1A The 74HC⁄HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power schottky... | |
| 25 ns (Typ.) Propagation Delay Time, 6.0 ns (Typ.) Fall Time, Quad 2 Input AND Gate ESD protection The devices are high speed si gate CMOS devices and are pin... | |
| 250 GATE ELECTRICALLY ERASABLE PLD, 20 PINS | |
| 3 V to 18 V, 500 mW, CMOS OR Gate Integrated Circuits Medium speed operation Standardized symmetrical output characteristics 5V, 10V, 15V parametric ratings Noise margin OR gates provide the... | |
| 5 V Voltage Supply, 500 ns (Max.) @ 4.5 V Input Rise Time, Quadruple 2-Input Positive-OR Gates Wide operating voltage range of 2 V to 6 V Outputs can drive... | |
| 5.0 V (Typ.) Supply Voltage, 500 mW (Max.) Power Dissipation, Quad 2-input NAND Gates Complies with JEDEC standard no. 8-1A The 74HC00⁄74HCT00 are high-speed Si-gate CMOS devices and are pin... | |
| 6.0 V (Max.) Supply Voltage, +⁄- 20 mA Clamp Diode Current, Quad 2-Input NAND Gates Complies with JEDEC standard no. 8-1A ESD protection: HBM EIA⁄JESD22-A114-A exceeds 2000 V, MM EIA⁄JES... | |
| 8-INPUT NAND GATE | |
| 9 ns (Typ.) Propagation Delay Time, 3.5 pF (Typ.) Input Capacitance, Quad 2-input NOR Gate Output capability: standard ICC category: SSI The 74HC⁄HCT02 are high-speed Si-gate CMOS devices and are... | |
| HEX SCHMITT TRIGGER, 14 Pin PDIP The MC14584B Hex Schmitt Trigger is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These devices find primary... | |
| QUAD 2-Input AND Gate, 3v to 18v, 260degc, 14 Pin Pdip, PB FREE The B Series logic gates are constructed with P and N channelenhancement mode devices in a single... | |
| AND GATE; CMOS-TTL; -0.5 TO 7 V; + 25 MA; 10 PF (MAX.); SOIC; | |
| BCD-To- Decimal Decoders⁄Drivers, Full Decoding Of Input Logic It consists of eight inverters and ten four input NAND Gates. This inverters are connected in pairs to make BCD input data... | |
| Circuit; 2-Input Positive NOR Gates; PDIP; 7 V; 0.1 mA; 2 V; 0.8 V; 8 mA (Max.) | |
| CMOS Construction, 18 V, 100 mW, 125 to 45 ns Propagation Delay, Logic NAND Gate Buffered inputs and outputs Standardized symmetrical output characteristics 100% tested for quiescent current at 20... | |
| CMOS Logic, 0 to +70 °C, Dual 4-Input Positive NAND Gates These devices contain two independent 4-input NAND gates. | |
| CMOS Logic, Dual 4-Input AND Gate, PDIP14, Pb-Free | |
| CMOS Logic, Dual 4-Input NAND Gate, PDIP14, Pb-Free | |
| CMOS Logic, Hex Inverter, PDIP14, Pb-Free | |
| CMOS Logic, Hex Inverter, SOIC14, Pb-Free | |
| CMOS Logic, Hex Schmitt-Trigger Inverter, PDIP14, Pb-Free | |
| CMOS Logic, NOR, NAND, Quad Inverter Gates, PDIP16, Pb-Free | |
| CMOS Logic, Quad 2-Input AND Gate, PDIP14, Pb-Free | |
| CMOS Logic, Quad 2-Input NAND Gate w/Schmitt-Trigger Inputs, PDIP14, Pb-Free | |
| CMOS Logic, Quad 2-Input NAND Gate, PDIP14, Pb-Free | |
| CMOS Logic, Quad 2-Input NAND Gate, SOIC14, Pb-Free | |
| CMOS Logic, Quad 2-Input NAND Gates with Schmitt Trigger, PDIP14, Pb-Free | |
| CMOS Logic, Quad 2-Input NOR Gate, PDIP14, Pb-Free | |
| CMOS Logic, Quad 2-Input OR Gate, PDIP-14, Pb-Free | |
| CMOS Logic, Quad 2-Input OR Gate, PDIP14, Pb-Free | |
| CMOS Logic, Quad Exclusive NOR Gates, PDIP14, Pb-Free | |
| CMOS Logic, Quad Exclusive OR Gates, PDIP14, Pb-Free | |
| CMOS Logic, Triple 3-Input AND Gate, PDIP14, Pb-Free | |
| CMOS Logic, Triple 3-Input NAND Gate, PDIP14, Pb-Free | |
| CMOS Logic, Triple 3-Input NOR Gate, PDIP14, Pb-Free | |
| CMOS LOGIC; 14 LD PDIP; EXCLUSIVE-OR GATES LOGIC; 0.5 TO 20V; -55; +125 | |
| CMOS QUAD 2-INPUT NOR GATE | |
| DECODER/DEMULTIPLEXE R; CMOS GATE; -0.5 TO .0 VDC; 5 VDC; 500 MW; 5 MADC | |
| DIP Pacakge, -0.5 V to +22 V Supply Voltage, Logic Quad 2 Input NAND Schmitt Trigger Schmitt trigger action on each input with no external components Hysteresis voltage typically 0.9V... | |
| DIP-14 Package, 5 V Supply Voltage, -40 To +125°C Temperature Range, Dual 4 Input AND Gates Low power dissipation Complies with JEDEC standard no. 7A ESD protection Specified The device... | |
| DUAL 4-INPUT NAND GATE | |
| Gate Logic IC, NAND QUAD 2INPUT 14-SOIC | |
| Gate Logic IC. Supply Voltage Min:2V, SMD; Package/Case:14-SOIC ; No. of Pins:14 | |
| GATE, AND/OR; PDIP; QUAD AND/OR GATE LOGIC; 20V; 500MW; -55; +125; 5 (TYP.) | |
| GATE, CMOS; CMOS; 20 V; 1 TO 6.8 MA (TYP.) (SINK); 500 MW; 7.5 (MAX.) PF; | |
| GATE, NAND; PDIP; NAND SCHMITT TRIGGER LOGIC; 20V; -55; +125V; 0.04 (TYP.) ICC | |
| GATE, NAND; QUADRUPLE 2-INPUT POSITIVE NAND GATE; PDIP; -40 DEGC; 85 DEGC | |
| GATE, NOR; QUADRUPLE 2 INPUT POSITIVE NOR GATE; PDIP; -40 DEGC; 85 DEGC | |
| GATE; SOIC; NAND FUNCTION LOGIC; 3 V (MIN.); 100MW; -55; +125; 5 PF (TYP.) | |
| Hex Inverter Buffers⁄Driver with Open Collector High-Voltage Outputs Convert TTL voltage levels to MOS levels High sink-current capability Input clamping diodes simplify system design Open-collector drivers for indicator lamps and... | |
| HEX SCHMITT-TRIG INV 14 PIN SOIC | |
| Hex, DIP-14 Package, 5 V (Typ.) Supply Voltage, -40 To +125°C Operating Temperature, Inverters Complies with JEDEC standard no. 8-1 A ESD protection Specified from -40 to +85°C and -40... | |
| IC GATE NAND QUAD 2INPUT 14DIP | |
| IC-CMOS AND GATE | |
| IC-CMOS NAND GATE | |
| IC-CMOS NOR GATE | |
| IC; PDIP; OR GATE FUNCTION LOGIC; 3 V TO 18 V; 500MW; -55; +125; 5; +265 | |
| IC; SOIC; OR GATE FUNCTION LOGIC; 3 V TO 18 V; 500MW; -55; +125; 5; +265 | |
| INVERTER, HEX; POSITIVE; 6 NS; 6 NS; PDIP-N; -40 DEGC; 85 DEGC | |
| INVERTER; TTL; -0.5 TO 7 V; 25 MA; 2 V (MIN.); 0.8 V (MAX.); -40 DEGC | |
| Logic Gate; Quad 2-Input OR; -0.5 to .0V | |
| LOGIC GATE; TTL; 14-LEAD PDIP; 7 V; 0.1MA; 2 V; 0.8 V; 3.4 V (TYP.) | |
| Logic, TTL, 8-Input Positive-NAND Gates, 5 Vss, PDIP-14 | |
| Low Power Schottky Barrier Diode, PDIP Package, 5 V Supply Voltage Improved line receiving characteristics High noise immunity Its operation from very slow edges. | |
| NAND Gate Logic, 10 V (Typ.) Supply Voltage, Integrated Circuit Audio Power Amplifier Low distortion Low quiescent current 34 dB internally fixed gain High input impedance Thermal overload protection Output... | |
| NAND GATE, QUADRUPLE 2-INPUT; NAND GATE; PDIP - N; 7 V; 2 V; 0.8 V; 0 TO DEGC | |
| NAND GATE, QUADRUPLE 2-INPUT; NAND GATE; PDIP; 7 V; 2 V; 0.8 V; -2 V (MIN.) | |
| NAND-GATE; TRIPLE 3 INPUT POSITIVE NANDGATE; 0 TO 5 V; 500 NS (MAX.) @ 4.5 V | |
| OR GATE; OR; 6 V (MAX.); 6 V (MAX.); 6 V (MAX.); 400 NS (MAX.) @ 6 V; SOIC-D | |
| PDIP Package Type, 5 V Voltage Supply, Hex Schmitt-Trigger Inverters Wide operating voltage range of 2 V to 6 V Outputs can drive up to 10 LSTTL loads Low power... | |
| PDIP Package Type, With 20 V Supply Voltage, CMOS 8-Input NAND⁄AND Gate Medium-speed peration Buffered inputs and outputs Noise margin The CD4068B types are sapplied in 14-lead hermetic Dual In... | |
| PDIP Package Type, With 20 V Supply Voltage, CMOS Quad Exclusive-OR Gate Medium speed operation Maximum input current Noise margin The CD4030B types are sapplied in 14-lead hermetic Dual In... | |
| PDIP, 5 V (Nom.), -40 to +85°C, 500 ns (Max.) @ 4.5 V, Quadruple 2 input positive AND Gates Fully static operation Buffered inputs common reset Balanced propagation delay and... | |
| PDIP-18 Package, -0.5 to +18.0 V Supply Voltage, BCD to Seven Segment Latch⁄Decoder⁄Driver Low logic circuit power dissipation High-current sourcing outputs Latch storage of binary input | |
| QUAD 2 IN NOR GATE, 14 PIN DIP | |
| Quad 2 Input, 2 To 6 V Supply Voltage, -40 TO +125°C Operating Temperature, NOR gates Output capability is standard ICC category of SSI The device are high speed si... | |
| Quad 2 input, DIP-14 Package, 5 V (Typ.) Supply Voltage, AND Gates ESD protection Specified from -40 to +85°C and -40 to +125°C. The device are high speed si gate... | |
| Quad 2 input, DIP-14 Package, 5 V (Typ.) Supply Voltage, AND Gates Wide supply voltage range from 2.0 to 6.0 V Symmetrical output impedance High noise immunity Low power dissipation... | |
| QUAD 2-INPUT EXCLUSIVE OR GATE | |
| Quad 2-input Exclusive-OR Gate SOIC Package, ICs Output capability is standard ICC category is SSI It is high-speed Si-gate CMOS devices and are pin compatible with low power schottky TTL... | |
| QUAD 2-INPUT EXCLUSIVE-OR GATE | |
| QUAD 2-INPUT NAND GATE OC | |
| QUAD 2-INPUT NOR GATE | |
| Quad, 2 Input, +5 V Supply Voltage, -40 To +125°C Operating Temperature, EXCLUSIVE-OR gates Output capability is standard ICC category of SSI The device are high speed si gate CMOS... | |
| Quad, 2 Input, +5 V Supply Voltage, -40 To +125°C Operating Temperature, NAND Schmitt Triggers Output capability is standard ICC category is SSI The device are high speed si gate... | |
| Quadruple 2-Input Positive AND Gate, 5 V Supply Voltage These devices contain independent 2 input AND Gate. | |
| Quadruple 2-Input Positive-OR Gate, PDIP Package Type, 5 V (NOM.) Supply Voltage Dependable Texas instruments quality and reliability These device contain four independent 2-input OR gates. | |
| Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs Wide operating voltage range of 2 V to 6 V outputs can drive up to 10 little loads Low power consumption, 20-uA max icc... | |
| SINGLE INVERTER GATE | |
| Supply 5.0 V (Typ.), -40 to +125°C, Input rise and fall time 6 ns, Hex inverting Schmitt trigger Wave and pulse shapers Astable multivibrators Monostable multivibrators. Complies with JEDEC standard... | |
| TRIPLE 3-INPUT AND GATE | |
| TRIPLE 3-INPUT NAND GATE | |
| TRIPLE 3-INPUT NOR GATE | |
| TRIPLE 3-INPUT OR GATE | |
| Triple 3-Input Positive NAND Gate, 14 Lead PDIP Package, 5 V (Typ.) Supply Voltage Dependable Texas Instrument quality and reliability | |
| Triple 3-Input Positive-AND Gate, HCMOS Logic, 2 to 6 V Supply Voltage, PDIP-N Package Type Wide operating voltage range of 2 V to 6 V Outputs can drive up to... | |
| TRIPLE 3-INPUT POSITIVE-AND GATES | |
| With 20 V Supply Voltage, CMOS Quad 2-Input NAND Schmitt Triggers Schmitt-trigger action on each input with no external components No limit on input rise and fall times Standardized, symmetrical... | |
| XOR GATE; XOR; 6 V (MAX.); 3.85 (MIN.) (HIGH) @ 5.5/1.65 (MAX.) (LOW) @ 5.5 V |