Gigabit Ethernet Transceiver -- KSZ9021




The KSZ9021 is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer Transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9021Gxx provides the industry standard Gigabit Media Independent Interface/Media Independent Interface (GMII/MII) for connection to GMII/MII MACs in Gigabit Ethernet Processors and Switches for data transfer at 1000Mbps or 10/100Mbps speed. The KSZ9021Rxx provides the Reduced Gigabit Media Independent Interface (RGMII).
The KSZ9021 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a LDO controller to drive a low cost MOSFET to supply the 1.2V core. The KSZ9021 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9021 I/Os and board. Micrel LinkMD® TDR-based cable diagnostics permit identification of faulty copper cabling. Remote and local loopback functions provide verification of analog and digital data paths.
The KSZ9021RL is available in a 64-pin, lead-free E-LQFP package, and is offered as the KSZ9021RN in the smaller 48-pin QFN package. The KSZ9021GN is available in a 64-pin, lead-free QFN package and the KSZ9021GQ is available in a 128-pin, lead-free PQFP package.
Microchip's complimentary and confidential LANCheck® online design review service is available for customers who have selected our products for their application design-in. The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.
Please consider this device KSZ9031
Additional Features
- Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet Transceiver
- KSZ9021G features GMII/MII standard compliant interface
- KSZ9021R features RGMII interface compliant to RGMII Version 1.3
- GMII/MII/RGMII I/Os with 3.3V/2.5V tolerant and programmable timings to adjust and correct delays on both Tx and Rx paths
- Auto-negotiation to automatically select the highest link up speed (10/100/100Mbps) and duplex (half/full)
- On-chip termination resistors for the differential pairs
- On-chip LDO controller to support single 3.3V supply operation – requires only external FET to generate 1.2V for the core
- Jumbo frame support up to 16KB
- 125MHz Reference Clock Output
- Programmable LED outputs for link, activity and speed
- Baseline Wander Correction
- LinkMD® TDR-based cable diagnostics for identification of faulty copper cabling
- Parametric NAND Tree support for fault detection between chip I/Os and board.
- Loopback modes for diagnostics