Clock and Data Distribution -- SY100S314




The SY100S314 offers five differential line receivers with emitter follower outputs, designed for use in high-performance ECL systems. For single-ended operation, the VBB reference voltage is available. In the single-ended mode, the apparent input threshold of the true inputs is 30mV higher than the threshold of the complementary inputs.Common mode rejection of +1.0V is achieved through the use of active current sources. If both the true and complement inputs are at the same potential between VEEand VCC, then the complementary outputs will take on a logic HIGH state. Unlike the other members of the High-Bandwidth 300K family, the inputs on this device do not have pull-down resistors.
Additional Features
- Max. propagation delay of 900ps
- Differential outputs
- IEE min. of -60mA
- Extended supply voltage option:
- VEE = -4.2V to -5.5V
- Voltage and temperature compensation for improved noise immunity
- VBB output for single-ended use
- More than twice as fast as National or Signetics
- Function and pinout compatible with National and Signetics F100K
- Available in 28-pin PLCC package