High-Bandwidth's SY69952 contains fully integrated transmitter and receiver functions designed to provide clock recovery and generation for either 51.84Mbit/s OC/STS-1 or 155.52Mbps OC/STS-3 SONET/SDH (SY69952) and ATM applications. On-chip clock generation is performed by a low-jitter phase-locked loop (PLL) allowing use of 19.44MHz reference for 155.52MHz generation or a 6.48MHz reference for 51.84MHz generation. Clock recovery is performed by synchronizing the on-chip VCO directly to the incoming data stream. The SY69952 meets the jitter compliance criteria of Bellcore, ITU/CCITT and ANSI standards. Low jitter is ensured by Micrel's advanced PLL technology and positive ECL (PECL) I/O. High-Bandwidth's circuit design techniques coupled with ASSET™ bipolar technology result in ultra-fast performance with low noise and low power dissipation.

Additional Features

• A complete ATM compatible single chip Transmitter and Receiver
• Seamless operation with PMC-Sierra PM5345, VLSI VNS67200, IgT WAC-013-B/WAC-413-A and NEC µPD98402 UNI Processors
• Supports clock and data recovery from 51.84Mbps or 155.52Mbps NRZ or NRZI data stream
• 155.52MHz clock multiplication from 19.44MHz source or 51.84MHz clock multiplication from 6.48MHz source
• Line Receiver Inputs: No external buffering needed
• Differential output buffering
• Link Status Indication
• Loop-back testing
• 100K ECL compatible I/O
• Single +5V power supply
• Replacement for Cypress CY7B952
• The SY69952 complies with Bellcore, ITU/CCITT and ANSI specifications
• Available in 28-pin SOIC package